Pixel sensors are known to comprise an array of sensor elements such as diodes, and a complementary array of electronics, typically in the form of an ASIC and comprising a charge amplifier and processing electronics for each sensor element. In CCDs such as are used in miniature television cameras and the like, the sensor elements are formed of silicon diodes which are responsive to visible light for producing a current which is amplified by the charge amplifier and subsequently processed.
Pixel sensors for X-ray and nuclear medical imaging are known that respond to high-energy photons such as X-rays or γ-rays and produce charge in a similar manner. Conventional silicon diodes are not suitable for such applications because they are transparent to the high-energy photons and therefore other materials such as cadmium telluride or mercuric iodide are used instead. Since these materials are not based on silicon, the diode cannot be integrated together with the associated electronics as a single monolithic structure and this requires, in practice, that the sensor elements and the associated electronics be manufactured on separate wafers, which are then interconnected using bump bonding.
Our prior application WO 03/083944 entitled “Pixel sensor array and method of manufacture thereof” and filed Feb. 18, 2003 discloses a sensor array having a plurality of pixels formed on a wafer 10 as shown in FIG. 1. The wafer 10 constitutes an integrated circuit or chip, typically formed of a complementary metal oxide semiconductor (CMOS) wafer and provided with scribe lines 11 so as to form a rectangular matrix of sensor elements 12 each of which, in turn, comprises a matrix of 3×5 pixels 13. The wafer 10 is processed at a silicon foundry in known manner and for the purpose of low-cost mass-production is processed according to the invention as an uncut wafer bearing multiple replicas of the same integrated circuit. Each pixel 13 includes a sensor input 14 that is connected to a charge amplifier 15 and a processing unit 16. The charge amplifier 15 together with the processing unit 16 constitute the pixel electronics to which the sensor element (not shown) is connected and which responds to a photon striking the sensor element for measuring the charge produced thereby. Thus, the silicon wafer 10 contains multiple replicas of the pixel array 12, and the silicon wafer 10, after scribing, would produce multiple ASICs each containing, for example, an array of 3×5 pixel electronic circuits for connecting to a respective sensor element.
In order to obviate the need for wire bonding as commonly used in pixel sensors, WO 03/083944 connects each sensor input 14 via a respective ohmic contact (or “via”) through the silicon wafer to the reverse side thereof. This contact may then be used to connect the sensor element directly to the sensor electronics by effectively bonding the sensor element in correct spatial disposition with respect to the electronics on the reverse side of the silicon wafer.
Reference is also made to “A vertically integrated high resolution active pixel sensor for deep submicron CMOS processes” by Stephan Benthien et al. presented to the IEEE Workshop on CCDs and Advanced Image Sensors, Jun. 10-12, 1999. This article describes a multi-pixel CMOS array for visible light applications, such as photography. It employs thin film ASIC (TFA) technology to deposit an amorphous silicon detector on a pre-fabricated ASIC. The article does not address the need for a multi-pixel sensor array that is amenable to formation of a large area sensor assembly having multiple sensor arrays juxtaposed and makes no provision for such assembly.
FIG. 2 shows pictorially a typical arrangement comprising a standalone 2-D pixel sensor depicted generally as 20 and comprising an upper sensor array 21 comprising multiple sensor elements (not shown), each of which is bump-bonded to a corresponding electronics module in a lower ASIC 22. In addition, power and control signals are fed to the sensor 20 and this typically requires that control-pads 23 be formed along at least one edge of the composite chip and which may be connected to external circuitry using wire-bonding 24.
The typical size of each pixel in such an array is 200 μm and the typical dimension of the two-dimensional array is 1 cm2. This means that there are typically some 625 pixels per pixel array. In practice, it is usually necessary to image over a much larger area, for example at least 10×10 cm2. This requires that 100 pixel arrays must be packed together, for example as a 10×10 matrix. On the one hand, the bump bonding technique used in conventional pixel sensors militates against the closer packing density of the pixels so that it becomes difficult to increase the resolution of the sensor by packing more pixels into a pixel array, since the need to bump-bond each sensor to the corresponding electronics in a different array is a costly process and is subject to low yields. Furthermore, the provision of control-pads along an edge of each module and the need to wire bond these pads to external circuitry means that adjacent sensor arrays cannot be packed edge-to-edge without introducing a “dead” zone where there are, in fact, no pixels at all owing to the interposing I/O and control-pads. Moreover, the connection of the I/O control-pads to the external circuitry by wire bonding is also a costly and cumbersome process and further reduces the effective overall packing density.
U.S. Pat. No. 5,254,868 (Yutaka) published Oct. 19, 1993 and entitled “Solidstate image sensor device” discloses a semiconductor image sensor device comprising arrayed photo-sensors, wherein a connection electrode used for connecting an external circuit or an aperture on the connection electrode is provided at an opposite side surface to an illuminated surface, and a transparent substrate is provided above the arrayed photo-sensors. By such means the distance between a light source and the photo-sensors can be reduced so as to improve sensitivity and resolving power.
U.S. Pat. No. 5,998,292 (Black et al.) issued Dec. 7, 1999 and entitled “Method for making three dimensional circuit integration” discloses a method for interconnecting, through high-density micro-post wiring, multiple semiconductor wafers with lengths of about a millimeter or below. The method comprises etching at least one hole, defined by walls, at least partly through a semiconducting material; forming a layer of electrically insulating material to cover said walls; and forming an electrically conductive material on said walls within the channel of the hole.
JP61 128564A2 (Fujitsu Ltd.) published Jun. 16, 1986 and entitled “Semi-conductor Device” describes a process for forming a photodetecting section and a driving circuit on the surface and the back of the same substrate and connecting both by a wiring through a through-hole. An amplifier and other driving circuits are shaped to a Si growth layer, and an n type region is formed through the implantation of B+ ions in order to shape a P-N junction for a photodetecting element. Aluminum for a wiring is shaped so as to unit one part of the n type region and the Si growth layer side where the driving circuit is formed, and shaped through a method, such as ion beam evaporation, electron beam evaporation, etc. while masking sections except a required section. Aluminum is evaporated from both upper and lower surfaces, and the wiring is connected by plating. An HgCdTe growth section in the photo-detecting element section and the Si growth layer are displaced, and formed on both surfaces of a sapphire substrate.
Such a configuration appears to relate to a single photo-detector only and the silicon is not pre-fabricated but rather is grown on top of the sapphire substrate.
EP1 045 450A2 (Agilent Technologies Inc.) published Oct. 18, 2000 and entitled “Image sensor array device” discloses an image sensor array that includes a substrate. An interconnect structure is formed adjacent to the substrate. An amorphous silicon electrode layer is adjacent to the interconnect structure. The amorphous silicon electrode layer includes electrode ion implantation regions between pixel electrode regions. The pixel electrode regions define cathodes of an array of image sensors. The electrode ion implantation regions provide physical isolation between the pixel electrode regions. The cathodes are electrically connected to the interconnect structure. An amorphous silicon I-layer is adjacent to the amorphous silicon electrode layer. The amorphous silicon I-layer forms an inner layer of each of the image sensors. A transparent electrode layer is formed adjacent to the image sensors. An inner surface of the transparent electrode layer is electrically connected to anodes of the image sensors and the interconnect structure. The amorphous silicon I-layer can further include I-layer ion implantation regions that provide physical isolation between the inner layers of the image sensors. The I-layer ion implantation regions align with the electrode ion implantation regions. An amorphous silicon P-layer can be formed adjacent to the amorphous silicon I-layer. The amorphous silicon P-layer forms an outer layer of each of the image sensors. The amorphous silicon P-layer can include P-layer ion implantation regions that provide physical isolation between the outer layers of the image sensors.
EP 537 514A2 (Mitsubishi corporation) published Apr. 21, 1993 and entitled “Optoelectronic integrated circuit” discloses an optoelectronic integrated circuit including a light receiving element for converting an optical signal to an electric signal and an electronic circuit for processing the electric signal. The light receiving element is disposed on a first main surface of the substrate and includes p side electrodes and n side electrodes alternately arranged in parallel to each other. The electronic circuit is disposed on a second main surface of the substrate. The light receiving element is electrically connected to the electronic circuit by a via hole penetrating through the substrate.
U.S. Pat. No. 4,547,792 (Sclar) issued Oct. 15, 1985 and entitled “Selective access array integrated circuit” discloses a semiconductor integrated circuit having an array of electronic devices and a plurality of electronic access devices. The access devices consist of sets of MOSFETs which may be turned on by the joint action of X and Y address lines to permit individual and isolated electrical connection between selected electronic devices in the array and peripheral on or off-hip sensing circuits. This permits continuous readout to be established and maintained for the selected devices without interference with the other devices in the array and without a requirement to readout any but the selected devices. In order to provide minimum dead space between the array detectors, the array and access devices may be disposed on opposite surfaces of the semiconductor body.
U.S. Pat. No. 4,857,746 (Werner et al.) issued Aug. 15, 1989 and entitled “Method for producing an optocoupler” discloses a method for manufacturing optocouplers or reflex light barriers, wherein semiconductor light transmitters and semiconductor light receivers are situated on a single substrate. The optic coupling or optic isolation of light transmitter and light receiver takes place in the substrate. Only then are semiconductor elements separated into discrete units.
Regardless of what technology is used to fabricate the sensor array, and regardless of the size of the sensor array, a practical CT detector typically requires that multiple sensor arrays be juxtaposed edge to edge in order to provide adequate coverage. Inevitably this introduces some “dead space” between adjacent sensor arrays which is insensitive to incoming photons as discussed above. It is clearly desirable to reduce the dead space as much as possible. The small size of hitherto-proposed sensor arrays such as shown in FIG. 2 having contact pads at an edge on the one hand militates against their use as standalone X-ray or γ-ray detectors and, on the other hand, renders it inevitable that when juxtaposed edge to edge there will be created dead spaces in the central regions of the detector which are insensitive to incoming photons.
Our WO 03/083944 as well as some of the other references discussed above address this problem and provide one solution: namely the provision of conductive vias so that connections to the sensor elements can be effected through the reverse side of the wafer. This solution is effective but the need to provide the conductive vias complicates the manufacturing process.
EP1253442A1 published Oct. 30, 2002 in the name of Hamamatsu Photonics and entitled “X-Ray image sensor” discloses a scintillator substrate constituted by an X-ray-transparent substrate and a scintillator in contact with the imaging plane of a solid-state imaging device. The solid-state imaging device and a frame are secured onto a base plate. The substrate is set relatively thin to improve its X-ray transmissivity.
U.S. Pat. No. 5,132,539 (Kwasnick et al.) published Jul. 21, 1992 and entitled “Planar X-ray imager having a moisture-resistant sealing structure” discloses a radiation imager comprising a scintillator mated to a photodetector array.
These prior art references are representative of X-ray imaging devices employing scintillators. These are not direct detection devices since their principle of operation is that incoming X-rays strike the scintillator where they produce light, which then strikes the adjacent photodetector array so as to generate spatial information relating to the position on the scintillator where the incident X-rays impinged. Such an approach is prone to inaccuracy since the light generated by the scintillator is apt to disperse and strike adjacent pixels of the photodetector array thereby resulting in poor spatial resolution. Moreover, scintillator detectors have poorer Detection Quantum Efficiency leading to higher patient dosage.
It would therefore be desirable to provide a large area sensor array suitable for that obviates the need to provide conductive vias through the silicon wafer, but nevertheless avoids dead space associated with know approaches and offers superior performance to scintillator detectors.